The use of electrostatic chucks in wafer processing systems is known. In wafer processing, wafers can be processed in a plasma processing system which may be used for etching (e.g., reactive ion etching RIE), oxidation, annodization, chemical vapor deposition (CVD), physical vapor deposition (PVD), and other processes associated with the manufacture of semiconductor wafers.
The plasma processing system typically includes a plasma processing chamber and one or more radio frequency (RF) (and/or direct current (DC)) power supplies. Within the plasma processing chamber, there may be disposed a shower head and an electrostatic chuck. The shower head is typically employed to distribute (process) gases into a plasma region of plasma processing chamber and may be made of a non-conductive material such as quartz.
When one or both of RF power supplies are energized, a plasma is created within a plasma region out of the source etchant gases. A wafer is disposed atop the electrostatic chuck to be processed by the plasma. The electrostatic chuck may be made of a suitable conductive material, such as an aluminum alloy, and may have any number of configurations. At the top surface of the electrostatic chuck, there is typically disposed a dielectric layer. Between the electrostatic chuck and the wafer, a heat transfer gas, e.g., helium, may be provided under pressure via a port to the wafer/chuck interface. The heat transfer gas acts as a heat transfer medium between the wafer and the electrostatic chuck to facilitate control of the wafer temperature during processing.
To securely clamp the wafer to the electrostatic chuck during processing, electrostatic forces are induced by a direct current power supply. In the case of a bipolar chuck, two poles may be biased with direct current potentials having opposite polarities. For example, one pole may be biased positively and another pole may be biased negatively. The direct current potential in each electrostatic pole creates a potential difference between the top surface of the pole and the corresponding overlying region in the bottom surface of the wafer, thereby generating an electrostatic force to hold the wafer to the electrostatic chuck.
When it is desired to remove the wafer from the chuck, a phenomenon called “wafer sticking” can sometimes occur. The phenomenon occurs when residual charge is left on the chuck dielectric or the wafer surface leading to undesired electric field and clamping force. This may arise because of uncompensated direct current (DC) bias and/or charge accumulated on the chuck surface or on the wafer due to excessive local field, which may cause field emission tunneling across the interface gap. Generally, charge is bled away when power is turned off to the electrostatic chuck. However, if charge does not go to zero or remains above a threshold value, the resulting residual charge may make it difficult to remove the wafer from the chuck. This sticking or de-chuck fault can create problems.
One problem created by the sticking is that the attempted lifting of the wafer off of the chuck can create “spray”. That is, sticking can cause the wafer to be subjected to stress during the de-chucking which can damage the wafer and result in “spray”. When pins in the chuck attempt to lift a sticky wafer off the chuck surface, particles of the wafer (and in particular from the edges of the wafer) may be broken off the wafer and these particles can be sprayed into the atmosphere of the processing chamber. Some of these particles can find their way onto the wafer surface. This can cause electrical opens due to block metal deposition. This “spray” is undesirable and is a symptom of sticking. The sticking, furthermore, is a symptom or an indicator of a possible SPC violation.
When it is desired to de-chuck the wafer, the power to the ESC is turned off so that the electrostatic force can be removed. However, this does not always occur and occasionally the wafer remains stuck to the ESC due to the presence of trapped charge within the ESC. The trapped charge may be due to the formation of a non-ohmic contact interface within the ESC. Trapped charge at potentials of (e.g., +50 to +150 volts) within the ESC causes substantial clamping force on the wafer. As a result, the wafer remains partially clamped even though the ESC power supply is in the “off” state. If the wafer is mechanically removed from the chamber while the ESC is in a partially clamped state, this can place stress on the wafer which causes mechanical damage and generates foreign material, commonly known as “ESC spray defects”.
Furthermore, RIE, CVD or PVD can impart a charge to the wafer due to ion bombardment of the wafer surface. Changes in the charge distribution across the surface of the wafer are measurable in the ESC bias and ESC current parameters. Plasma instabilities, charging and electrostatic discharge within the reaction chamber create temporal disturbances to ion flux to the wafer, which, in turn cause corresponding changes to the wafer charge distribution, that are measureable as changes in the ESC bias and ESC current. These and other plasma perturbations can lead to temporal distortions in the plasma flux, causing surface charge rearrangement as measurable in the ESC bias and ESC current.
For example, the electrostatic (arc) discharges are particularly problematic within RIE, CVD, and PVD processes that result in temporal disturbances to the ion flux reaching the wafer surface. Disturbances in the ion flux cause disturbances in the charge distribution across the wafer that are measurable in the ESC bias and ESC current parameters. Similarly, an arc discharge to the wafer can damage the wafer and can create a perturbation in the wafer surface charge distribution, resulting in current flow into or out of the ESC. That is, the arc can create a spike in the ESC bias as well as a spike in the ESC current. Such spikes in the ESC bias and ESC current are undesirable and are a symptom or indicator of a possible SPC violation. That is, they can be indicative of a problem with the processing tool specifically a charge buildup within the tool and subsequent high voltage discharge at or near the wafer. This results in physical damage to the internal components of the reactor, physical damage to the wafer and electrical damage to the semiconductor devices present on or within the wafer.
Although conventional RIE, CVD and PVD processing tools currently provide information about the ESC bias voltage and current, this information is not utilized to determine whether the power subsystems, ESC and other internal reactor components, (and by extension the processing tool) is functioning properly, and/or is not utilized to determine whether wafers produced by a processing tool could possibly be in violation of SPC.
In view of the foregoing, there is a need for improved methods and apparatuses or systems for preventing sticking and/or for determining when a processing tool is processing wafers which have failed, are likely to fail, or will soon fail or result in an SPC violation. That way, the processing tool can be flagged for repair or maintenance to correct the possible problems with, e.g., the chuck and/or shower head. Furthermore, the processing tool can be bypassed so that no wafers are processed by the possibly malfunctioning processing tool until it is repaired or otherwise brought into conformance with SPC requirements.